Method ShiftRightLogical_Core
- Namespace
- Zyl.VectorTraits.Impl.AVector256
- Assembly
- VectorTraits.dll
ShiftRightLogical_Core(Vector256<sbyte>, int, Vector256<sbyte>, Vector256<sbyte>)
Core calculation for shifts (unsigned) each element of a vector right by the specified amount. (将向量的每个无符号元素逻辑右移指定量的核心计算). Its arguments are derived from ShiftRightLogical_Args (其参数来源于 ShiftRightLogical_Args).
Mnemonic: rt[i] := value[i] >>> shiftAmount
, shiftAmount &= (T.BitSize-1)
.
[CLSCompliant(false)]
public virtual Vector256<sbyte> ShiftRightLogical_Core(Vector256<sbyte> value, int shiftAmount, Vector256<sbyte> args0, Vector256<sbyte> args1)
Parameters
value
Vector256<sbyte>The vector whose elements are to be shifted (要移位其元素的向量).
shiftAmount
intThe number of bits by which to shift each element (每个元素的移位位数).
args0
Vector256<sbyte>Arguments 0 (参数0). Derived from ShiftRightLogical_Args .
args1
Vector256<sbyte>Arguments 1 (参数1). Derived from ShiftRightLogical_Args .
Returns
- See Also
ShiftRightLogical_Core(Vector256<byte>, int, Vector256<byte>, Vector256<byte>)
Core calculation for shifts (unsigned) each element of a vector right by the specified amount. (将向量的每个无符号元素逻辑右移指定量的核心计算). Its arguments are derived from ShiftRightLogical_Args (其参数来源于 ShiftRightLogical_Args).
Mnemonic: rt[i] := value[i] >>> shiftAmount
, shiftAmount &= (T.BitSize-1)
.
public virtual Vector256<byte> ShiftRightLogical_Core(Vector256<byte> value, int shiftAmount, Vector256<byte> args0, Vector256<byte> args1)
Parameters
value
Vector256<byte>The vector whose elements are to be shifted (要移位其元素的向量).
shiftAmount
intThe number of bits by which to shift each element (每个元素的移位位数).
args0
Vector256<byte>Arguments 0 (参数0). Derived from ShiftRightLogical_Args .
args1
Vector256<byte>Arguments 1 (参数1). Derived from ShiftRightLogical_Args .
Returns
- See Also
ShiftRightLogical_Core(Vector256<short>, int, Vector256<short>, Vector256<short>)
Core calculation for shifts (unsigned) each element of a vector right by the specified amount. (将向量的每个无符号元素逻辑右移指定量的核心计算). Its arguments are derived from ShiftRightLogical_Args (其参数来源于 ShiftRightLogical_Args).
Mnemonic: rt[i] := value[i] >>> shiftAmount
, shiftAmount &= (T.BitSize-1)
.
public virtual Vector256<short> ShiftRightLogical_Core(Vector256<short> value, int shiftAmount, Vector256<short> args0, Vector256<short> args1)
Parameters
value
Vector256<short>The vector whose elements are to be shifted (要移位其元素的向量).
shiftAmount
intThe number of bits by which to shift each element (每个元素的移位位数).
args0
Vector256<short>Arguments 0 (参数0). Derived from ShiftRightLogical_Args .
args1
Vector256<short>Arguments 1 (参数1). Derived from ShiftRightLogical_Args .
Returns
- See Also
ShiftRightLogical_Core(Vector256<ushort>, int, Vector256<ushort>, Vector256<ushort>)
Core calculation for shifts (unsigned) each element of a vector right by the specified amount. (将向量的每个无符号元素逻辑右移指定量的核心计算). Its arguments are derived from ShiftRightLogical_Args (其参数来源于 ShiftRightLogical_Args).
Mnemonic: rt[i] := value[i] >>> shiftAmount
, shiftAmount &= (T.BitSize-1)
.
[CLSCompliant(false)]
public virtual Vector256<ushort> ShiftRightLogical_Core(Vector256<ushort> value, int shiftAmount, Vector256<ushort> args0, Vector256<ushort> args1)
Parameters
value
Vector256<ushort>The vector whose elements are to be shifted (要移位其元素的向量).
shiftAmount
intThe number of bits by which to shift each element (每个元素的移位位数).
args0
Vector256<ushort>Arguments 0 (参数0). Derived from ShiftRightLogical_Args .
args1
Vector256<ushort>Arguments 1 (参数1). Derived from ShiftRightLogical_Args .
Returns
- See Also
ShiftRightLogical_Core(Vector256<int>, int, Vector256<int>, Vector256<int>)
Core calculation for shifts (unsigned) each element of a vector right by the specified amount. (将向量的每个无符号元素逻辑右移指定量的核心计算). Its arguments are derived from ShiftRightLogical_Args (其参数来源于 ShiftRightLogical_Args).
Mnemonic: rt[i] := value[i] >>> shiftAmount
, shiftAmount &= (T.BitSize-1)
.
public virtual Vector256<int> ShiftRightLogical_Core(Vector256<int> value, int shiftAmount, Vector256<int> args0, Vector256<int> args1)
Parameters
value
Vector256<int>The vector whose elements are to be shifted (要移位其元素的向量).
shiftAmount
intThe number of bits by which to shift each element (每个元素的移位位数).
args0
Vector256<int>Arguments 0 (参数0). Derived from ShiftRightLogical_Args .
args1
Vector256<int>Arguments 1 (参数1). Derived from ShiftRightLogical_Args .
Returns
- See Also
ShiftRightLogical_Core(Vector256<uint>, int, Vector256<uint>, Vector256<uint>)
Core calculation for shifts (unsigned) each element of a vector right by the specified amount. (将向量的每个无符号元素逻辑右移指定量的核心计算). Its arguments are derived from ShiftRightLogical_Args (其参数来源于 ShiftRightLogical_Args).
Mnemonic: rt[i] := value[i] >>> shiftAmount
, shiftAmount &= (T.BitSize-1)
.
[CLSCompliant(false)]
public virtual Vector256<uint> ShiftRightLogical_Core(Vector256<uint> value, int shiftAmount, Vector256<uint> args0, Vector256<uint> args1)
Parameters
value
Vector256<uint>The vector whose elements are to be shifted (要移位其元素的向量).
shiftAmount
intThe number of bits by which to shift each element (每个元素的移位位数).
args0
Vector256<uint>Arguments 0 (参数0). Derived from ShiftRightLogical_Args .
args1
Vector256<uint>Arguments 1 (参数1). Derived from ShiftRightLogical_Args .
Returns
- See Also
ShiftRightLogical_Core(Vector256<long>, int, Vector256<long>, Vector256<long>)
Core calculation for shifts (unsigned) each element of a vector right by the specified amount. (将向量的每个无符号元素逻辑右移指定量的核心计算). Its arguments are derived from ShiftRightLogical_Args (其参数来源于 ShiftRightLogical_Args).
Mnemonic: rt[i] := value[i] >>> shiftAmount
, shiftAmount &= (T.BitSize-1)
.
public virtual Vector256<long> ShiftRightLogical_Core(Vector256<long> value, int shiftAmount, Vector256<long> args0, Vector256<long> args1)
Parameters
value
Vector256<long>The vector whose elements are to be shifted (要移位其元素的向量).
shiftAmount
intThe number of bits by which to shift each element (每个元素的移位位数).
args0
Vector256<long>Arguments 0 (参数0). Derived from ShiftRightLogical_Args .
args1
Vector256<long>Arguments 1 (参数1). Derived from ShiftRightLogical_Args .
Returns
- See Also
ShiftRightLogical_Core(Vector256<ulong>, int, Vector256<ulong>, Vector256<ulong>)
Core calculation for shifts (unsigned) each element of a vector right by the specified amount. (将向量的每个无符号元素逻辑右移指定量的核心计算). Its arguments are derived from ShiftRightLogical_Args (其参数来源于 ShiftRightLogical_Args).
Mnemonic: rt[i] := value[i] >>> shiftAmount
, shiftAmount &= (T.BitSize-1)
.
[CLSCompliant(false)]
public virtual Vector256<ulong> ShiftRightLogical_Core(Vector256<ulong> value, int shiftAmount, Vector256<ulong> args0, Vector256<ulong> args1)
Parameters
value
Vector256<ulong>The vector whose elements are to be shifted (要移位其元素的向量).
shiftAmount
intThe number of bits by which to shift each element (每个元素的移位位数).
args0
Vector256<ulong>Arguments 0 (参数0). Derived from ShiftRightLogical_Args .
args1
Vector256<ulong>Arguments 1 (参数1). Derived from ShiftRightLogical_Args .
Returns
- See Also